Field of the Invention
The present invention relates to a memory control circuit for controlling a memory device that operates in a self-refresh mode and a method of controlling the same, and, for example, to a memory control circuit for controlling a volatile memory device, such as an SDRAM.
Description of the Related Art
In a typical computer hardware architecture, a memory device is controlled by a memory controller which controls writing of data into the memory device and readout of the data from the memory device, during normal operation thereof. Some memory devices can operate in a self-refresh mode in which the memory device maintains the stored data even when the memory controller is powered off. Note that the memory device refers to an integrated circuit (IC) memory device chip, and the memory controller refers to an IC memory controller chip.
In a memory device formed by a DDR2-SDRAM, by setting a clock enable (CKE) signal to be input to the memory device to a low level, it is possible to power off the memory controller while holding the memory device in the self-refresh mode. This is because a RESET signal is not input to the DDR2-SDRAM, and hence the DDR2-SDRAM can operate only with a CKE signal when the memory controller is started from the power-off state or returning from the self-refresh mode.
On the other hand, in some of other memory devices, a RESET signal is input. Particularly, in a memory device formed by a DDR3-SDRAM, a RESET signal is input when starting from the power-off state. Therefore, if the memory controller is powered off in the self-refresh mode, it is impossible to hold the self-refresh mode when starting the memory controller after that. That is, this causes a problem that data stored in the memory device in the self-refresh mode cannot be preserved.
As a solution to this problem, there has been proposed a method of operating a memory control circuit including a memory device, a memory controller, a power module, and a reset controller (see e.g. Japanese Patent Laid-Open Publication No. 2010-262645). In this method, the memory controller controls the normal operation of the memory device by applying a clock enable signal to a CKE input of the memory device. This CKE input is further connected to a CKE termination node to which electric power is supplied by the power module such that it has a CKE termination voltage.
With this configuration, a power-down operation for powering down the memory control circuit is performed in such a procedure that the memory controller drives the CKE signal to a low level, the power module powers down the CKE termination voltage, and then the power module powers down the memory controller. On the other hand, the normal operation of the memory control circuit is restarted after the power-down in such a procedure that first, the power module powers up the memory controller, then, the memory controller drives the CKE signal to a low level, and the power module powers up the CKE termination voltage.
According to these procedures, it is guaranteed that the memory device remains in the self-refresh mode after the memory control circuit is powered down until the normal operation is restarted.
However, in the method disclosed in Japanese Patent Laid-Open Publication No. 2010-262645, a memory reset controller as part of the memory controller cannot be powered off, and hence although the memory control circuit can be powered down, it cannot be powered off. This is because if the memory reset controller is powered off, the memory reset signal control becomes unstable, which prevents the memory device from being held in the self-refresh mode, and jeopardizes the integrity of the data stored in the memory device.